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IS23SC1604 integrated silicon solution, inc. 1-800-379-4774 1 advance information nv002-0d 01/19/99 issi ? this document contains advance information data. issi reserves the right to make changes to its products at any time without no tice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1999, integrated silicon solution, inc. IS23SC1604 16-kbit secured serial eeprom advance information january 1999 features ? 16k serial eeprom with security features ? comply with iso/iec standard 7816-3 synchronous protocol ? store and validate security codes ? four protected application zones ? provide transport code security ? single 5v power supply for read/write/erase operations ? low power operation: C 8 m a (max.) standby current C 3 ma (max.) read current at 300 khz C 4 ma (max.) write/erase current ?2 m s read access time at 300 khz; 5 ms write cycle time ? 300 khz serial clock rate ? high esd protection: > 4 kv ? high reliability: C 1,000,000 erase/write cycles C 10 years data retention ? standard cmos process ? wide operating temperature range C 0 to +70 c commercial; C40 to +85 c industrial ? data access only after validation of security code ? permanent invalidation of device upon eight consecutive failed attempts to enter the correct security code ? separate read/write/erase access protections for each application zone ? allow the memory chip to be personalized if the internal security fuse is not blown. if the internal security fuse is blown, maximum security protec- tion of the memory will always be enabled. description IS23SC1604 is a low-cost, low-power, highly secured 16k bits (2k x 8) serial eeprom. it is fabricated using issis advanced cmos technology. the security features of IS23SC1604 provide high levels of memory security protection for smart card applications. the memory is partitioned into four application zones. each individual application zone is protected by multiple security codes from unauthorized read/write/erase access to the zone. in addition, an internal security fuse is available for the card issuer to fully personalize the device before releasing it to customer. the device also features an internal high-voltage charge pump for memory programming, 1,000,000 write/erase cycles and ten years of data retention. figure 1. pin configuration: 8-pin plastic dip c1 c2 c3 c4 c5 c6 c7 c8 vcc rst clk fus gnd nc i/o pgm issi ?
IS23SC1604 2 integrated silicon solution, inc. 1-800-379-4774 advance information nv002-0d 01/19/99 issi ? i/o (open drain) pgm power on reset high- voltage generator address decoder 2007 x 8 eeprom security logic clk fus rst vcc gnd (internal pull-downs on clk, fus, and pgm and internal pull-up on rst) figure 2. block diagram
IS23SC1604 integrated silicon solution, inc. 1-800-379-4774 3 advance information nv002-0d 01/19/99 issi ? pin names (1) iso pad pad name description c1 8 vcc supply voltage c2 7 rst reset c3 6 clk serial clock and address control c4 5 fus security fuse pad c5 4 gnd ground c6 3 nc no connect c7 2 i/o bi-directional data c8 1 pgm programming control note: 1. pins clk, fus, and pgm have internal pull-downs. pin rst has an internal pull-up. pin descriptions symbol type card contact name and function vcc c1 supply voltage rst c2 reset: the device's rst pin can be used to clear the internal address counter. when clk is low, a high-to-low transition on rst resets the address counter to zero, and the first bit of memory will be output on i/o after the falling edge of rst. also, the rst pin can be used to place the device in low power standby mode by placing rst in high logic state and both pgm and fus in low logic state. while rst is high, the internal address counter will not be incremented with clk. clk c3 serial clock and address control: this is the device data clock pin. it is used to clock data bits into and out of the device. it also increments the internal address counter. fus c4 security fuse pad: this pin is used by card issuer to personalize the device before releasing it to the customer. when fus pin is driven to logic high state and the state of the internal security fuse is high (not blown), the issuer can personalize the entire content of the memory with successful security code (sc) validation. when fus pin is driven to logic low state and the state of the internal security fuse is high (not blown), the full protection of the memory is enabled and the security features of the device can be tested by the issuer. after the device personalization is completed, the issuer should blow the internal security fuse to logic low state so that the full protection of the memory will always be enabled regardless of the state on fus pin. (refer to IS23SC1604 security levels and also blowing internal security fuse.) gnd c5 ground nc c6 no connect i/o c7 serial data input and output: this pin is where the data bit is shifted in and out of the device when a clock pulse is applied to clk pin. pgm c8 programming control: this pin is asserted high to initiate memory write or erase operation.
IS23SC1604 4 integrated silicon solution, inc. 1-800-379-4774 advance information nv002-0d 01/19/99 issi ? IS23SC1604 operations power-on reset (por) when the supply voltage is first applied to the device, the device initiates por. all the internal flags are clear (refer to definition of IS23SC1604 internal flags ), and the internal address counter is reset to zero. reset with clk low, a high-to-low transition at rst resets the address counter to zero. after the falling edge of rst, the device outputs the first bit of the memory on i/o pin. the reset operation will have no effect on any internal flags (see figure 3). addressing addressing is handled by an internal address counter which is incremented on the falling edge of clk. when the counter continues to increment past 16383, the counter will roll over back to zero. the counter can also be cleared to zero by the reset operation. read if read access to a memory bit is enabled, the state of the bit can be read out of the device by incrementing the address counter to the bit location. the device outputs the state of the read bit on the i/o pin after the falling edge of the last clock pulse that increments the address counter to the read bit location. however, if the read access to the memory bit is inhibited, the state of the data bit will not be output and the i/o pin will be placed in high-impedance state 1 (see figure 4). compare compare operation allows users to input the security/erase key code for the security/erase key code validation for read/ write/erase access to protected application zones (refer to security/erase key code validation operation). the compare operation latches the users input security/ erase key bit into the device at the rising edge of clk and the bit comparison is performed on the next falling edge of clk. the compare and read operations are executed in the same manner. the device distinguishes between the two operations by testing the address counter for security/erase key code location and the state of corresponding security/ erase key code valid comparison flag (see figure 5). write if write access to a memory bit is enabled, the content of the bit can be written over with a 0 value by performing the following sequence: select pgm (logic high state), input 0 on the i/o pin, change clk from low-to-high, deselect pgm (logic low state), wait for 5 ms programming delay, and then bring clk down from high-to-low to complete the write operation. the new state of the bit will be output at the end of the write operation after the falling edge of clk for data verification (see figure 6). erase if erase access to a memory bit is enabled, the content of the bit can be written over with a 1 value with the erase operation. although erase is performed on single bits, the erase operation writes ffh to the whole byte which contains the erased bits because the memory is organized into 8-bit bytes. the erase operation can be executed by performing the following sequence: select pgm (logic high state), input 1 on the i/o pin, change clk from low-to-high, deselect pgm (logic low state), wait for 5 msec programming delay, and then bring clk down from high- to-low to complete the erase operation. the new state of the bit will be output at the end of the erase operation after the falling edge of clk for data verification (see figure 6).
IS23SC1604 integrated silicon solution, inc. 1-800-379-4774 5 advance information nv002-0d 01/19/99 issi ? table 1. device operations (1) operation fus pgm rst clk description reset x x 0 the address counter is reset to zero and the first bit of the memory is output after the falling edge of rst. inc/read x 0 0 the address counter is incremented and the first bit is output after the falling edge of the clock if read access to the bit location is en- abled. inc/cmp x 0 0 compare the input bit with the internal bit of the memory (for security/erase key codes valida- tion). the address counter is incremented on the falling edge of clk. the input bit is latched into the device at the rising edge of clk and the bit comparison is done on the next falling edge of clk. erase/write x 1 0 for write operation (write a 0 to the current address), a 0 is placed on i/o before the rising edge of clk. for erase byte operation (write ffh to the byte that contains the current bit), a '1' is placed on i/o before the rising edge of clk. clk must stay high for 5 ms during memory programming. verify x 0 0 the new content of the curent address will be output after the falling edge of clk for verifica- tion. standby 0 0 1 x the device is placed into standby mode. in this mode, the address counter will not be incremented with clock pulse when rst is high. note: 1. x = don't care.
IS23SC1604 6 integrated silicon solution, inc. 1-800-379-4774 advance information nv002-0d 01/19/99 issi ? electrical characteristics absolute maximum ratings (1) symbol parameter min. max. unit vcc supply voltage C0.3 6 v v i / v o input/output voltage C0.3 6 v t stg storage temperature C40 125 o c p max power dissipation 60 mv note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range range ambient temperature vcc commercial 0 to +70 c5v industrial C40 to +85 c5v capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 c, v cc = 5.0v + 10%; gnd = 0v, f = 1 mhz. dc electrical characteristics (1) (t a = 0 to 70 c, vcc = 5.0 + 10%, gnd = 0v ) symbol parameter test condtions min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v i cc supply read/compare current t a = 25 c, 3.0 ma f clk = 300 khz i ccp supply write/erase current t a = 25 c 4.0 ma i ccsb standby supply current t a = 25 c, 8.0 m a rst = 5v; fus, clk, pgm = 0v, i io = 0 m a v il input low level C0.3 0.8 v v ih input high level 2.0 vcc + 0.3 v v ol output low level i ol = 1 ma 0.4 v i li input leakage current 50 m a i lh i/o leakage current v oh = 5v open drain 50 m a note: 1. there is a internal pull-up on pin rst. there are internal pull-downs on pins fus, clk, and pgm
IS23SC1604 integrated silicon solution, inc. 1-800-379-4774 7 advance information nv002-0d 01/19/99 issi ? ac test conditions parameter value input pulse levels gnd to 3.0v input rise and fall time 5 ns input and output timing and reference level 0.8v and 2.0v output load 100 pf ac electrical characteristics (t a = 0 to 70 c, vcc = 5.0v + 10%; gnd = 0v) symbol parameter min. typ. max. unit f clk clock frequency 300 khz t clk clock cycle time 3.3 m s t rh rst hold time 0.1 m s t dvr data valid reset to address 0 2.0 m s t ch clk pulse width (high) 0.2 m s t cl clk pulse width (low) 0.2 m s t dv data access 2.0 m s t oh data hold 0 m s t sc data in setup (cmp instruction) 0 m s t hc data in hold (cmp instruction) 0.2 m s t chp clk pulse width (high in erase/write) 5.0 ms t ds data in setup 0.2 m s t dh data in hold 0 m s t spr pgm setup 2.2 m s t hpr pgm hold 0.2 m s i/o gnd test point chip 100 pf 4.7k w figure 3. ac test load circuit
IS23SC1604 8 integrated silicon solution, inc. 1-800-379-4774 advance information nv002-0d 01/19/99 issi ? figure 4. reset timing diagram address address = 0 output data valid rst t rh t dvr clk i/o address output data valid ax ax + 1 t clk clk i/o t dv t oh t oh figure 5. read timing diagram
IS23SC1604 integrated silicon solution, inc. 1-800-379-4774 9 advance information nv002-0d 01/19/99 issi ? address input data valid input data valid the bit compare is performed on the falling edge of clk. data is latched into the device on the rising edge of clk. ax clk i/o t sc t hc t hc figure 6. compare timing diagram t oh t oh t dv i/o t hpr t spr t dv t chp read verify program t dh t ds t dh address out valid data out valid data input data valid ax ax ax+1 clk pgm figure 7. write/erase timing diagram
IS23SC1604 10 integrated silicon solution, inc. 1-800-379-4774 advance information nv002-0d 01/19/99 issi ? table 2. memory map start bit end bit start byte end byte symbol description address address bits address address bytes fz fabrication zone 0 15 16 0 1 2 iz issuer zone 16 79 64 2 9 8 sc security code 80 95 16 10 11 2 scac security code attempts counter 96 103 8 12 12 1 cpz code protected zone 104 167 64 13 20 8 application 1 sc1 application zone 1 security code 168 183 16 21 22 2 s1ac application zone 1 sc1 attempts counter 184 191 8 23 23 1 ez1 application zone 1 erase key 192 207 16 24 25 2 e1ac application zone 1 ez1 attempts counter 208 215 8 26 26 1 az1 application zone 1 216 9775 9560 27 1221 1195 application 2 sc2 application zone 2 security code 9776 9791 16 1222 1223 2 ez2 application zone 2 erase key 9792 9807 16 1224 1225 2 e2ac application zone 2 ez2 attempts counter 9808 9815 8 1226 1226 1 az2 application zone 2 9816 11863 2048 1227 1482 256 application 3 sc3 application zone 3 security code 11864 11879 16 1483 1484 2 ez3 application zone 3 erase key 11880 11895 16 1485 1486 2 e3ac application zone 3 ez3 attempts counter 11896 11903 8 1487 1487 1 az3 application zone 3 11904 13951 2048 1488 1743 256 application 4 sc4 application zone 4 security code 13952 13967 16 1744 1745 2 ez4 application zone 4 erase key 13968 13983 16 1746 1747 2 e4ac application zone 4 ez4 attempts counter 13984 13991 8 1748 1748 1 az4 application zone 4 13992 16039 2048 1749 2004 256 mtz memory test zone 16040 16055 16 2005 2006 2 total addressable eeprom memory 16056 2007 fuse internal security fuse 16288 16303 last bit address 16383 IS23SC1604 memory map IS23SC1604 memory is divided into four application zones. each application zone has a corresponding access security code, access attempts counter (only application zone 1), erase key, erase attempts counter, and data storage area.below is the memory map table for IS23SC1604:
IS23SC1604 integrated silicon solution, inc. 1-800-379-4774 11 advance information nv002-0d 01/19/99 issi ? application zone erase keys attempts counter (e1ac, e2ac, e3ac, e4ac) counts number of failed attempts to input the correct application zone erase key to the device. after eight consecutive failed attempts, the erasure of the corresponding application zone will never be allowed (refer to memory access table). application zones (az1, az2, az3, az4) each application zone provides protected data storage space for user application. the read, write and erase access to the application zone are controlled by the first two bits of the zone as well as the corresponding application zone security code and application zone erase key and the security code (refer to memory access table). memory test zone (mtz) there are no protections on this zone. IS23SC1604 security levels there are two security levels available in IS23SC1604 which are controlled by the internal security fuse state and fus pin. at security level 1, the issuer has access to the entire memory with successful security code (sc) validation and the issuer is allowed to personalize the content of the entire memory except the fabrication zone (fz). at security level 2, the memory is fully protected by various security codes in the memory. when the card has been personalized, the internal security fuse should be blown to protect the card memory from unauthorized usage before the card is released to the customer (refer to blowing internal security fuse ). once the security fuse is blown, it cannot be changed again. below is the truth table that shows how the security level can be set with the state of fus input pin. table 3. security levels fus pin state of the internal fuse security level gnd dont care 2 v cc high (fuse not blown) 1 v cc low (fuse blown) 2 IS23SC1604 memory partitions fabrication zone (fz) this zone is programmed by the manufacturer. after the zone is programmed, the manufacturer disables the write/ erase access to this zone so that it cannot be changed by card issuer or card user. issuer zone (iz) this zone can only be programmed by the issuer during device personalization process. security code (sc) this code serves as master security password to access to devices memory. a special transport code is programmed into sc location by the manufacturer and it is only made known to the issuer. this special code secures the transport of the device between the manufacturer and the issuer. after the issuer successfully validates the transport code, sc can be freely altered as wished. after the internal security fuse is blown, sc protects the access to the four application zones of the device. security code attempts counter (scac) counts number of failed attempts to input the correct security code (sc) to the device. after eight consecutive failed attempts, the device will be locked permanently. code protected zone (cpz) this zone is read access only. access to erase or write to this zone is protected by security code (sc). application zone security codes (sc1, sc2, sc3, sc4) these codes protect access to individual application zones of the memory. application zone security code attempts counter (s1ac) counts number of failed attempts to input the correct application zone 1 security code to the device. after eight consecutive failed attempts, the application zone 1 will be locked permanently. application zone erase keys (ez1, ez2, ez3, ez4) these keys protect individual application zones (az1, az2, az3, az4) from unauthorized attempt to erase the zone.
IS23SC1604 12 integrated silicon solution, inc. 1-800-379-4774 advance information nv002-0d 01/19/99 issi ? IS23SC1604 internal flags the IS23SC1604s internal flags enable/disable the read, write, and erase access to application zones (refer to memory access table). all the flags are clear upon power- on reset (por). the flags can be set to logic 1 state by validating the corresponding security code through the validation process. once the flag is enabled (1 state), it cannot be cleared by any operations except por. security code valid comparison flag (sv) this flag is set to 1 after the security code (sc) is validated (see figure 7). this flag protects an unpersonalized card from unauthorized usage. if the card has already been personalized, this flag provides master protection for the application zones (refer to memory access table). application zone 1 security code valid comparison flag (s1) this flag is set to 1 after the application zone 1 security code (sc1) is validated (see figure 7). this flag provides access protection for application zone 1 (refer to memory access table). application zone m security code valid comparison flag (sm) where m = 2, 3 or 4. this flag is set to 1 after the application zone m security code is validated (see figure 8). this flag provides access protection for application zone m (refer to memory access table). application zone n erase key valid comparison flag (sn) where n = 1, 2, 3 or 4. this flag is set to 1 after the application zone n erase key is validated (see figure 7). this flag provides protection for application zone n from unauthorized erasure of the zone (refer to memory access table). application zone n write flag (pn) where n = 1, 2, 3 or 4. this flag is set to 1 if the first bit of application zone n is 1 (bit address: 216 for zone 1, 9816 for zone 2, 11904 for zone 3, or 13992 for zone 4). this flag enables write access to the corresponding application zone (refer to memory access table). application zone n read flag (rn) where n = 1, 2, 3 or 4. this flag is set to 1 when the second bit of application zone n is 1 (bit address: 217 for zone 1, 9817 for zone 2, 11905 for zone 3, or 13993 for zone 4). this flag enables read access to the corresponding application zone (refer to memory access table).
IS23SC1604 integrated silicon solution, inc. 1-800-379-4774 13 advance information nv002-0d 01/19/99 issi ? rst i/o (mode) clk pgm fz, iz, b. read a. reset operation address security/erase code zone (16-bits) security/erase code attempts counter c. compare d. read e. write i. read h. verify f. verify t chp t chp g. erase out security/erase code flag out out out in in out out out out out out out out in 0 000 0 111 0 1 2 in in in figure 8. security/erase key code validation security/erase key code validation operation (for sc, sc1, ez1, ez2, ez3, and ez4 validation) a) reset the address counter to zero. b) send required number of clock pulses to increment the address counter to security/erase key code location. c) input the security/erase key code bit by bit for code validation. d) after security/erase key code entry, look for the first logic 1 bit in security/erase key code attempts counter. if the 1 bit is found, do not increment the address. e) write a 0 over the 1 bit in security/erase key code attempts counter at the current bit location. f) the chip outputs a 0 after programming is done. g) if the security/erase key code validation was successful, the corresponding comparison flag will be set to 1 on the rising edge of pgm and the security/erase key code attempts counter should be erased to reactivate the eight allowable attempts. (the validation operation can be aborted by setting clk high when pgm is still low.) h) if the comparison flag were successfully set to 1, the erasure of the attempt counter would be allowed and the device would output a 1 on i/o after the erase operation. otherwise, the erasure of the attempt counter would be blocked and a 0 would be output on i/o. (the content of the attempt counter remains unchanged.) i) on the following edge of the clock, the address counter is incremented and the state of the next bit is output on i/o. notes: 1. the address counter does not increment from steps e to h. 2. after eight consecutive failed attempts to validate the security/erase key code, the corresponding flag will be locked at 0 permanently.
IS23SC1604 14 integrated silicon solution, inc. 1-800-379-4774 advance information nv002-0d 01/19/99 issi ? rst i/o (mode) clk fz, iz, b. read a. reset security/erase code zone (16-bits) c. and d. compare e. read out security/erase code flag out out out out in in in in in 0 1 2 operation address figure 9. application zone security code validation a) reset the address counter to zero. b) send required number of clock pulses to increment the address counter to application zone security code location. c) input the application zone security code bit by bit for code validation. application zone security code validation operation (for sc2, sc3, and sc4 validation) d) if the security code validation were successful, the corresponding comparison flag would be set to 1. e) on the following edge of the clock, the address counter is incremented and the state of the next bit is output on i/o.
IS23SC1604 integrated silicon solution, inc. 1-800-379-4774 15 advance information nv002-0d 01/19/99 issi ? rst i/o (mode) clk pgm fz, iz, a. read reset internal fuse b. and c. write d. verify t chp out internal fuse state out out out out in out out 00 16288 0 0 1 1 2 operation address figure 10. blowing internal security fuse a) set the address counter between 16288 and 16303. b) set fus pin at v cc or gnd; set rst pin at v cc . c) write 0 to the current bit location. d) the chip outputs a 0 after programming is done. the state of the internal security fuse is now 0 (blown state). note: 1. sv flag must be enabled (high state) to blow the internal security fuse. blowing internal security fuse
IS23SC1604 16 integrated silicon solution, inc. 1-800-379-4774 advance information nv002-0d 01/19/99 issi ? memory access table table 4. memory access conditions at security level 1 (device personalization) erase write fields sv rn read (write 1) (write 0) compare fz x x yes no no no iz 0 x yes no no no 1 x yes yes yes no sc 0 x no no no yes 1 x yes yes yes no scac 0 x yes no yes no 1 x yes yes yes no cpz 0 x yes no no no 1 x yes yes yes no scn 0 x no no no no 1 x yes yes yes no s1ac 0 x yes no no no 1 x yes yes yes no ezn 0 x no no no no 1 x yes yes yes no enac 0 x yes no no no 1 x yes yes yes no azn 0 0 no no no no 0 1 yes no no no 1 x yes yes yes no mtz x x yes yes yes no note: 1. n corresponds to application zone n where n = 1, 2, 3, or 4. security level one at security level one (security fuse not blown and fus pad at v cc ), the memory access is controlled by security code valid comparison flag (sv) and application zone n read flag (rn).
IS23SC1604 integrated silicon solution, inc. 1-800-379-4774 17 advance information nv002-0d 01/19/99 issi ? memory access table security level two at security level two (security fuse blown or fus pad at gnd), memory access is controlled by sv, sn, pn, rn and en flags. table 5. memory access conditions at security level 2 (product release) erase write fields sv sn pn rn en read (write 1) (write 0) compare fz x x x x x yes no no no iz x x x x x yes no no no sc 0 x x x x no no no yes 1 x x x x no yes yes no scac 0 x x x x yes no yes no 1 x x x x yes yes yes no cpz 0 x x x x yes no no no 1 x x x x yes yes yes no scn 0 x x x x no no no no 1 0 x x x no no no yes 1 1 x x x no yes yes no s1ac 0 x x x x yes no no no 1 0 x x x yes no yes no 1 1 x x x yes yes yes no ezn 0 x x x x no no no no 10xx0nononono 1 1 x x 0 no no no yes 1 1 x x 1 no yes yes no enac 0 x x x x yes no no no 1 0 x x 0 yes no no no 1 1 x x 0 yes no yes no 1 1 x x 1 yes yes yes no aznx0x0xnononono x 0 x 1 x yes no no no 1 1 0 x 0 yes no no no 1 1 0 x 1 yes yes no no 1 1 1 x 0 yes no yes no 1 1 1 x 1 yes yes yes no mtz x x x x x yes yes yes no note: 1. n corresponds to application zone n where n = 1, 2, 3, or 4.
IS23SC1604 18 integrated silicon solution, inc. 1-800-379-4774 advance information nv002-0d 01/19/99 issi ? ordering information commercial range: 0 c to +70 c order part number package IS23SC1604-x2 sorted wafer IS23SC1604-x3 dice in waffle pack after backgrinding to 8-9 mil. IS23SC1604-x4 dice in waffle pack after backgrinding to 10-11 mil. IS23SC1604-x5 sorted wafers on a ring IS23SC1604-x6 individual modules IS23SC1604-x7 taped modules IS23SC1604-x8 blank cards IS23SC1604-p 300-mil plastic dip industrial range: C40 c to +85 c order part number package IS23SC1604-x2i sorted wafer IS23SC1604-x3i dice in waffle pack after backgrinding to 8-9 mil. IS23SC1604-x4i dice in waffle pack after backgrinding to 10-11 mil. IS23SC1604-x5i sorted wafers on a ring IS23SC1604-x6i individual modules IS23SC1604-x7i taped modules IS23SC1604-pi 300-mil plastic dip issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com

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